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preliminary datasheet TLE6288 r vp2 page 1 13.01.2003 tle 6288 r : smart 6 channel peak&hold switch features product summary ? 3 channel high side with adjustable p&h current control ? 3 channel high / low side configurable ? protection over current (current limitation) overtemperature overvoltage (active clamping) ? diagnosis over current over temperature open load (off-state) short to ground (off-state, lowside configura- tion) short to vbb (off-state, highside configura- tion) ? interface and control 16 bit serial peripheral interface (2bit/ch) device programming via spi separate diagnosis output for each ch ( diag1 ? 6) general fault flag + overtemperature flag direct parallel control of all channels general enable signal to control all channels simultaneously ? low quiescent current ? compatible with 3.3v and 5v microcontrollers ? e lecto s tatic d ischarge (esd) protection of all pins application ? solenoids, relays and resistive loads ? fast protected highside switching (pwm up to >10khz) ? peak and hold loads (valves, coils) general description the TLE6288 r is a 6-channel (150m ? ) smart multichannel switch in spt4 tech- nology. the ic has embedded protection, diagnosis and configurable functions. channel 1-3 are highside channels with integrated charge pump and can be pro- grammed individually to do autonomous peak and hold current regulation with pwm. channel 4-6 (also with integrated charge pump) can be configured to work as highside switch or lowside switch. this ic can be used to drive standard automo- tive loads in highside or lowside applica- tions with switching frequencies up to 10khz. in addition the TLE6288r can be used to drive autonomously up to 3 induc- tive peak&hold (valves, coils) loads with programmable peak and hold current val- ues. supply voltage v s 4.5 ? 5.5 v on resistance r on 1-6 0.15 ? lowside clamping voltage v cll (max) +55 v highside clamping voltage v clh (max) -19 v peak current range i pk 1.2 - 3.6 a hold current range i hd 0.7 - 2 a peak time range i p 0 - 3.6 ms fixed off time range i fo 100 ? 400 s p-dso 36-12 ordering code: charge- pump vcp gnd fsin channel 1-3 highside 150 m peak&hold channel 4 -6 highside/ lowside 150 m ? vcc dout 3 / vb sout 1 spi sclk cs si so logic configuration in 1 diag 1 diag 5 in 6 diag 6 overtemp. reset vdo clkprog fault dout 1 protection diagnosis protection diagnosis sout 3 dout 6 sout 4 dout 4 sout 6 sout 2 dout 2 sout 5 dout 5 current regulation
preliminary datasheet TLE6288 r vp2 page 2 13.01.2003 1. block diagram charge pump vcp gnd fsin channel 3 highside 300 m ? peak&hold channel 2 highside 300 m ? peak&hold channel 1 highside 300 m ? peak&hold channel 4 highside/ lowside 300 m ? channel 5 highside/ lowside 300 m ? channel 6 highside/ lowside 300 m ? vb vcc dout 3 / vb sout 3 sout 2 sout 1 dout 4 sout 4 dout 5 sout 5 dout 6 sout 6 spi sclk cs si so logic driver diagnosis in 1 diag 1 in 2 in 3 in 4 in 5 diag 5 in 6 diag 6 overtemp. reset vdo clkprog fault . . vcc vcc . vcc . . vcc . . . . . . . gnd gnd dout 2 dout 1
preliminary datasheet TLE6288 r vp2 page 3 13.01.2003 2. functional description block diagram will be added channel 1..3: only high side drive with charge pump. current control default 2.4a peak and 1a hold with adjustable values by spi types of current control are switched by spi. ( refer to fig. 1) current regulation: peak current controller with fixed off-time peak current, peak time, hold current and off-time can be selected by spi to set average and ripple current for a given load channel 4..6: either high or low side drive is configurable (by spi) open load detection and switch bypassed detection can be deactivated by spi
preliminary datasheet TLE6288 r vp2 page 4 13.01.2003 protection: the TLE6288r has integrated protection functions 1 for overload and short circuit (active current limitation), overtemperature, esd at a ll pins and overvoltage at the power outputs (zener clamping). output stage control: parallel control and spi control a boolean operation (either and or or) is performed on each of the parallel inputs in 1..6 and respec- tive spi data bits, in order to determine the states of the respective outputs. the type of boolean op- eration performed is programmed via the serial interface. both, parallel inputs and respective spi da- tabits are high active. truth table parallel input spi bit output or output and 0 0 off off 0 1 on off 1 0 on off 1 1 on on each output is independently controlled by an output latch and a common reset line fsin, which dis- ables all outputs. a logic high input ?data bit? turns the respective output channel on, a logic low ?data bit? turns it off. overtemperature behavior: each channel has an overtemperature sensor and is individually protected against overtemperature. as soon as overtemperature occurs the channel is immediately turned off. in this case here are two different behavoirs of the affected channel that can be selected by spi (for all channels generally). autorestart : as long as the input signals of the channel remains on (e.g. parallel input high) the chan- nel turns automatically on again after cooling down. latching : after overtemperature shutdown the channel stay s off until the this ovetemperature latch is reset by a new l ? h transition of the input signal. note: these overtemperature sensors of the channels are only active if the channel is turned on. an additional overtemperature sensor is located in the logic of the device. i monitors permanently the ic temperature. as soon as the ic temperature r eaches a specified level an overtemperature fault will be indicated. 1 integrated protection functions are designed to prevent ic destruction under faul t conditions described in the data sheet. faul t conditions are considered as "outside" normal operating range. protection functions are not des igned for continuous repetitive operation . or and output driver in 1?6 serial input bits 6 -11 of command ?channels on / off ?
preliminary datasheet TLE6288 r vp2 page 5 13.01.2003 current regulator : peak current control with fixed off-time hold only : when the channel is turned on externally (spi or parallel input) the current rises to the pro- grammed hold current level. then the channel is internally turned off and a timer is started for a con- stant off-time (e.g. 200s). after this time the channel is internally turned on again until the hold current level is reached again and so on. this regulation workes automatically until the channel is turned of externally. peak and hold mode with minimum peak time: when the channel is turned on the current rises to the programmed peak current level. then the channel is internally turned off, the current regulator changes to hold current values and a timer is started for a constant off-time. after this time the channel is inter- nally turned on again until the hold current value is reached and then again turned off for the fixed off time. this regulation workes automatically until the channel is turned of externally. peak and hold mode with programmed peak time: when the channel is turned on the current rises to the programmed peak current level. then the channel is internally turned off and a timer is started for a constant off-time. after this time the channel is internally turned on again until the peak current value is reached and then again turned off. this works until the programmed peak time is over. then the cur- rent regulator changes to hold current values and workes as described under "hold only". peak current, peak time, hold current and fixed off-time can be set via spi. to avoid regulation disturbances by current transient s during switching (e.g. caused by esd capacitors at the outputs) the current regulator has a "leading edge blanking" of typical 20s in all three regulation modes. after turning on the dmos (internally or exte rnally) the current regulation circuit is deactivated for the first 20s. this guarantees that switching of t he dmos itself or charging of small capacitors at the output (e.g. esd) is not disturbing the current regulation. simplified functional block diagram:
preliminary datasheet TLE6288 r vp2 page 6 13.01.2003 current waveforms of the different current control modes peak and hold with set peak time hold only peak & hold with min. peak time i hd i hd i pk i pk t p t fo no regulation current defined only by load input signal i hd t fo t fo t fo fig.1 current forms of the different current control modes of channel 1-3
preliminary datasheet TLE6288 r vp2 page 7 13.01.2003 3. pin configuration pin nr. name function pin nr. name function 1 sout4 source output ch 4 (high / low side) 19 sout3 source output ch 3 (high side) 2 dout4 drain output ch 4 (high / low side) 20 dout3 drain output ch 3(high side) 3 dout1 drain output ch 1(high side) 21 vcp charge pump pin 4 sout1 source output ch 1 (high side) 22 fsin all channels enable / disable 5 in4 control input channel 4 23 gnd logic ground 6 in1 control input channel 1 24 fault general fault flag 7 diag1 diagnostic output ch 1 25 in3 control input channel 3 8 diag2 diagnostic output ch 2 26 in6 control input channel 6 9 diag3 diagnostic output ch 3 27 reset reset pin (+ standby mode) 10 diag4 diagnostic output ch 4 28 vcc logic supply voltage (5v) 11 diag5 diagnostic output ch 5 29 vdo supply pin for digital outputs 12 diag6/overtemp diagnostic output ch 6 / overtemp 30 so spi serial data output 13 in2 control input channel 2 31 clkprog program pin of spi clock 14 in5 control input channel 5 32 sclk spi serial clock 15 sout2 source output ch 2 (high side) 33 cs spi chip select 16 dout2 drain output ch 2(high side) 34 si spi serial data input 17 dout5 drain output ch 5 (high / low side) 35 dout6 drain output ch 6 (high / low side) 18 sout5 source output ch 5 (high / low side) 36 sout6 source output ch 6 (high / low side) package: power-p-dso-36 0.65mm pitch in4 in1 sout4 dout4 dout1 sout1 diag1 diag2 diag5 dia6/overtemp sout2 dout2 dout5 sout5 in2 in5 reset in6 sout6 dout6 si _cs sclk clk prog so vdo vcc gnd fsin vcp dout3 sout3 in3 fault 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 27 26 25 24 23 22 21 20 19 36 35 34 33 32 31 30 29 28 TLE6288 r (s0999) diag3 diag4
preliminary datasheet TLE6288 r vp2 page 8 13.01.2003 4. pin description: dout 1-3 ? drain of the 3 highside channels. these pins must always be connected to the same power (battery) supply line. sout 1-3 ? source of the three highside channels. outputs of the highside channels where the load is connected. dout 4-6 ? drain pins of the three configurable channels. in highside configuration they must be con- nected to the same voltage as dout 1-3. in lowside configuration they are the output pins and con- nected to the load. sout 4-6 ? source of the three configurable channels. in highside configuration they are the outputs and connected to the load. in lowside configuration they must be connected with gnd. in 1-6 ? parallel input pins for the 6 power outputs. these pins have an internal pull down structure. gnd ? logic ground pin. fsin ? disable pin. if the fsin pin is in a logic low state, it switches all outputs off. an internal pull-up structure is provided on chip. reset ? reset pin. when the reset is low all channels are off, the internal biasing is deactivated, all internal registers are cleared and the supply-current consuption is reduced (standby mode). an internal pull-up structure is provided on chip. fault ? general fault pin. there is a general fault pin (open drain) which shows a high to low transition as soon as an error is latched into the diagnosis register. when the diagnosis register is cleared this flag is also reset (high state). this fault indication can be used to generate a c interrupt. clkprog ? programming pin for the spi clock signal. this pin can be used to configure the clock sig- nal input of the spi. in low state the spi will read data at the rising clock edge and write data at the falling clock edge. in high state the spi will read data at the falling clock edge and write data at the ris- ing clock edge the pin has an internal pull down structure. diag1..5; diag6 / overtemp. ? parallel diagnostic pins (push-pull) change state according to the in- put signal of the corresponding channel. as soon as an error occurs at the corresponding channel ( overload and overtemperature is detected in on st ate and open load /switch bypass in off state) the diag output shows the inverted input signal. an fault is detected only if it lasts for longer than the fault filtering time. the fault information is not latched in a register. if diag6 is configured as overtemperature flag: this is a general fault pin which shows a high to low transition as soon as an overtemperature error occurs for any one of the six channels (for longer than the fault filtering time) or the ic logic. this fault indication can be used to differ between overload and overtemperature errors in one of the six channel s or to detect a general ic overtemperature. vcp ? pin to connect the external capacitor of the integrated charge pump. vdo ? supply pin of the push-pull digital output drivers. this pin can be used to vary the high-state output voltage of the so pin and the diag1-6 pins. vcc ? logic supply pin. this pin is used to supply the integrated circuitry. cs ? chip select of the spi so ? signal output of the s erial p eripheral i nterface si ? signal input of the s erial p eripheral i nterface. the pin has an internal pull down structure. sclk ? clock input of the s erial p eripheral i nterface. the pin has an internal pull up structure (if clkprog=l) or an pull down structure (if clkprog=h). for more details about the spi see chapter 9.spi.
preliminary datasheet TLE6288 r vp2 page 9 13.01.2003 5. maximum ratings no. parameter symbol value unit pin / comment 1 power supply voltage 1 static dynamic : 1min. 0c dynamic : test cond. fig.1 v b v b v b -0.3 ?20 24 37 v v v dout1-3 dout1-3 dout1-3 2 power supply voltage 2 v cc , v do - 0.3 ... 7 v vcc, vdo 3a continuous drain source voltage (lowside configuration) v dsl 40 v dout ? sout (channel 4-6) 3b continuous source voltage (highside configuration) v sh -9 ... v b v sout - gnd (channel 4-6) 4 input voltage v in -0.3 ? v cc + 0.3 v in1-6, reset, fsin, cs, sck, si, clkprog 5a output voltage v out -0.3 ? v cc + 0.3 v fault 5b output voltage v out -0.3 ? v do + 0.3 v diag1-6, so 5c output voltage v cp out v b +10 v vcp ; no voltage must be applied 6 operating temperature t a t j -40 ? +105 -40 ? +150 c c 7 storage temperature t stg -55 ? +150 c 8 power dissipation (r thja = 20k/w) (r thja = 30k/w) p dmax 2,25 1,5 w 9 reverse current (1ms) i rev -4 a between dout and- sout; channel 4 to 6 10 esd (human body model) c= 100pf, r=1.5k ? applied to all terminals 3 times v esdb 2000 v 11 esd (machine model) c= 200pf, r=0 ? applied to all terminals 3 times v esdm 250 v 12 single switch off load inductance see fig.2 dout, sout test cond. fig.1 12v 37v 10 times (once/ 30sec) 160ms 350ms fig.2 added after characterisation
preliminary datasheet TLE6288 r vp2 page 10 13.01.2003 6. electrical characteristics v cc = 4.5 to 5.5 v ; t j = - 40 c to + 150 c ; v b = 6v to 16v ; reset = h ; v do = v cc (unless otherwise specified) value no. parameter sym- bol condition min typ max unit pin / comment 1 power supply, reset 1.1 power supply current 1 i b ch1-ch6: off 10 ma dout1-3 1.2 power supply current 2 i cc 10 ma vcc 1.3 power supply current 3 in standby mode i cc +i b reset = l 50 a dout1-3, vcc 1.4 minimum reset duration t re- set,min 50 s 1.5 wake up time after reset t wakeup c cp = 10 nf 5 ms 2 power outputs 2.1 on resistance r ds(on) i d =2.4a v b =10v 350 m ? doutx ? soutx 2.2 forward voltage revers diode v rdf i d = -4a t j = 150c 2 v soutx ? doutx 2.3 peak current range i pk 1.2 -- 3.6 a 2.4 peak current accuracy i pka tj= 25, 150 tj=-40 15 20 % 2.5 hold current range i hd 0.7 -- 2 a 2.6 hold current accuracy i hda tj= 25, 150 tj=-40 15 20 % 2.7 peak time range t p 0.8 -- 3.6 ms 2.8 peak time accuracy t pa 20 % 2.9 fixed off time range t fo 100 - - 400 s 2.10 fixed off time accuracy t foa 100s 30 % 2.11 fixed off time accuracy 200s- 400s 20 %
preliminary datasheet TLE6288 r vp2 page 11 13.01.2003 v cc = 4.5 to 5.5 v ; t j = - 40 c to + 150 c ; v b = 6v to 16v ; reset = h ; v do = v cc (unless otherwise specified) value no. parameter sym- bol condition min typ max unit pin / comment 2.12 output on delay time1 t don fig.3 10 s 2.13 output on rise time1 t r fig.3 10 s 2.14 output off delay time1 t doff fig.3 hs- mode ls- mode 20 20 s 2.15 output off fall time1 t f fig.3 10 s 2.16 leackage current reset = l 10 a 2.17 leak current in off (highside configuration) i loff -250 a sout1-6 2.18 leak current in off (lowside configuration) i loff 500 a dout4-6 2.19 output clamp voltage highside configuration v clh referes to gnd level -9 -14 -19 v sout1-6 2.20 output clamp voltage lowside configuration v cll referes to gnd level 40 55 v dout4-6 2.21 current limitation (channel 1-3) i dlim1-3 4 6 a 2.22 current limitation (channel 4-6) i dlim4-6 3 6 a 2.23 ic overtemp. warning hysteresis t ot t hys 160 10 180 c c 3 digital inputs 3.1 input low voltage v inl 1 v all digit. inputs 3.2 input high voltage v inh 2 v all digit. inputs 3.3 input voltage hysteresis v inhys 100 mv all digit. inputs 3.4 input pull down current i pd v in = 5v 20 50 100 a in1-6; clkprog 3.5 input pull up current i pu v in = gnd 20 50 100 a reset; fsin 3.6 spi input pull down current i pd v in = 5v 10 20 50 a si, sclk (clkprog=h) 3.7 spi input pull up current i pd v in = gnd 10 20 50 a cs;sclk (clkprog=l)
preliminary datasheet TLE6288 r vp2 page 12 13.01.2003 v cc = 4.5 to 5.5 v ; t j = - 40 c to + 150 c ; v b = 6v to 16v ; reset = h ; v do = v cc (unless otherwise specified) value no. parameter sym- bol condition min typ max unit pin / comment 4 digital outputs 4.1 so low state output voltage v sol i sol =2.5ma 0.4 v so 4.2 so high state output voltage v soh i soh =-2ma v do - 0.4v v so 4.3 diag low state output voltage i diagl = 50a 0.4 v diag1-6 4.4 diag high state output voltage i diagh = -50a v do - 0.4v v diag1-6 4.5 fault low output voltage v ol i out = 1ma 0.4 v fault 4.6 fault output leak current i oh output :off v (fault) =5v 1 a fault 5 diagnostic functions 5.1 open load detection voltage v ds(ol) lowside con- figuration, vbat=12v 5.5 v 5.2 open load detection voltage v ds(ol) highside configura- tion, vbat=12v 4.5 v 5.3 output open load diag- nosis current i d(ol) vbat=vout= 12v 20 100 500 a 5.4 fault filter time t f(fault) 50 100 200 s 5.5 switch bypass detec- tion current i d(sb) 250 a 5.6 overload detection threshold (channel 1-3) i dd(lim1- 3) 4 6 a 5.7 overload detection threshold (channel 4-6) i dd(lim 4- 6) 3 6 a fig.3 : turn on/off timings with resistive load input voltage output voltage (highside configuration) 70% 30% t don t doff t r t f
preliminary datasheet TLE6288 r vp2 page 13 13.01.2003 v cc = 4.5 to 5.5 v ; t j = - 40 c to + 150 c ; v b = 6v to 16v ; reset = h ; v do = v cc (unless otherwise specified) value no. parameter sym bol condition min typ max unit pin / comment 6 spi timing 6.1 serial clock frequency (de- pending on so load) f sck dc -- 5 mhz 6.2 serial clock period (1/fclk) t p(sck) 200 -- -- ns 6.3 serial clock high time t sckh 50 -- -- ns 6.4 serial clock low time t sckl 50 -- -- ns 6.5 enable lead time (falling edge of cs to falling edge of sclk) t leadl clkprog=l 200 -- -- ns enable lead time (falling edge of cs to rising edge of sclk) t leadh clkprog=h 200 -- -- ns 6.6 enable lag time (rising edge of sclk to rising edge of cs ) t lagl clkprog=l 200 --- -- ns enable lag time (falling edge of sclk to rising edge of cs ) t lagh clkprog=h 200 --- -- ns 6.7 data setup time (required time si to rising of sclk) t sul clkprog=l 20 -- -- ns data setup time (required time si to falling of sclk) t suh clkprog=h 20 -- -- ns 6.8 data hold time (rising edge of sclk to si) t hl clkprog=l 20 -- -- ns data hold time (falling edge of sclk to si) t hh clkprog=h 20 -- -- ns 6.9 disable time t dis -- 200 ns 6.10 transfer delay time 2 ( cs high time between two accesses) t dt 200 -- -- ns 6.11 data valid time c l = 50 pf to 100pf c l = 220 pf t valid -- -- -- -- 120 150 ns 1) to get the correct diagnostic information, the transfer del ay time has to be extended to the maximum fault delay time t f(fault)max = 200s.
preliminary datasheet TLE6288 r vp2 page 14 13.01.2003 7 diagnostics detailled description of the diagnosis will be added 8 spi the spi is a s erial p eripheral i nterface with 4 digital pins and an 16 bit shift register. the spi is used to configure and program the device, turn on and off channels and to read detailled diagnostic information. 8.1 spi signal description: cs - chip select. the system microcontroller selects the tle 6288 r by means of the cs pin. when- ever the pin is in a logic low state, data can be transferred from the c and vice versa. cs = h : any signals at the sclk and si pins are ignored and so is forced into a high impedance state. cs = h ? l : ? diagnostic information is transferred from the diagnosis register into the spi shift register. ? serial input data can be clocked into the spi shift register from then on ? so changes from high impedance state to logic high or low state corresponding to the so bits cs = l : spi is working like a shift register. with each clock signal the state of the si is read into the spi shift-register and one diagnosis bit is written out of so. cs = l ? h: ? transfer of si bits from spi shift register into the internal logic registers ? reset of diagnosis register if sent command was valid to avoid any false clocking the serial clock input pin sclk should be logic high state (if cklprog=l; low state if clkprog=h) during high to low transition of cs . sclk - serial clock. the serial clock pin clocks the internal spi shift register of the tle 6288 r. the serial input (si) accepts data into the input spi shift register on the rising edge of sclk (if cklprog=l; falling edge if clkprog=h) while the serial output (so) shifts diagnostic information out of the spi shift register on the falling edge (if cklprog=l; rising edge if clkprog=h) of serial clock. it is essential that the sclk pin is in a logic high state (if cklprog=l; low state if clkprog=h) whenever chip select cs makes any transition. si - serial input. serial data bits are shifted in at this pin, the most significant bit (msb) first. si infor- mation is read in on the rising edge of sclk (if cklprog=l; falling edge if clkprog=h). input data is latched in the spi shift register and then transferred to the internal registers of the logic. the input data consist of 16 bit, made up of 4 control bits and 12 data bits. the control word is used to program the device, to operate it in a certain mode as well as providing diagnostic information (see spi commands). so - serial output. diagnostic data bits are shifted out serially at this pin, the most significant bit (msb) first. so is in a high impedance state until the cs pin goes to a logic low state. new diagnostic data will appear at the so pin following the falling edge of sclk (if cklprog=l; rising edge if clkprog=h). spi cs sclk si so internal logic registers diagnosis register 16 bit spi shift register si so cs cs msb msb lsb lsb serial input data msb first serial output (diagnosis) msb first
preliminary datasheet TLE6288 r vp2 page 15 13.01.2003 8.2 spi diagnostics: as soon as a fault occurs for longer than the fault filtering time, the fault information is latched into the diagnosis register (and the fault pin will change from high to low state). a new error on the same channel will over-write the old error report. serial data out pin (so) is in a high impedance state when cs is high. if cs receives a low signal, all diagnosis bits can be shifted out serially. if the sent com- mand was valid the rising edge of cs will reset the diagnosis registers (except the channel ot flag) and restart the fault filtering time. in case of an invalid command the device will ignore the data bits and the diagnosis register will not be reset at the rising cs edge. figure 1: two bits per channel diagnostic feedback plus two overtemperature flags for full diagnosis there are two diagnostic bits per channel configured as shown in figure 1. diagnosis bit0 and bit1 are always set to 1. normal function: the bit combination hh indicates that there is no fault condition, i.e. normal function. overload, shorted load or overtemperature: hl is set when the current limitation gets active, i.e. there is a overload, short to supply or overtemperature condition. the second reason for this bit combi- nation is overtemperature of the corresponding channel. open load: lh is set when open load is detected (in off state of the channel) switch bypassed: short to gnd : in lowside configuration ll is set when this condition is detected short to battery : in highside configuration ll is set when this condition is detected channel overtemperature flag: in case of overtemperature in any output channel in on state the overtemperature flag in the spi diagnosis register is set (change bit 3 from 0 to 1). this bit can be used to distinguish between overload and overtemperature (both hl combination) and is reset by switching off/on the affected channel. in addition the diag6 / ovtertemp pin is set low (if configured as overtemp.flag). ic overtemperature flag: when the ic logic tremperature exceeds typ.170 the non-latching ic overtemperature flag will be set in the spi diagnosis register(change bit 2 from 0 to 1). in addition the diag6 / ovtertemp pin is set low (if configured as overtemp.flag). 8.3 spi commands, values and parameters: diagnostic serial data out so hh normal function hl overload, shorted load or overtemperature lh open load ll switch bypassed ch.6 ch.5 ch.4 ch.3 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 msb ch.2 ch.1 lsb channel overtem- perature flag ic overtem- perature flag bit0 and bit1 is always 1
preliminary datasheet TLE6288 r vp2 page 16 13.01.2003 si so cs 4 bits 12 bits command da ta diagnosis ( ch. 1 to 6) + 2 temp. flags si command : 4 command bits program the operation mode of channels 1 to 6. 12 data bits configure the device and give the input information (on or off) for channel 1 to 6. so diagnosis 16 bit diagnosis information (two bit per channel) of channels 1 to 6 plus two overtemperature flags the 16 bit spi is used to program different ic functions and values, turn on and off the channels and to get de- tailled diagnosis information. therefore 4 command bits and 12 data bits are used. the following parameters and functional behavior can be programmed by spi: current regulation mode (mode) : for each of the three highside channels individually the operation mode can be set. a) "no current regulation b) current regulation "hold only c) current regulation "peak & hold with minimum peak time d) current regulation "peak & hold with pro- grammed peak time". peak current (i pk ) : for each of the three highside channels individually the peak current value for p&h current regulation can be programmed. the current range is 1.2a to 3.6a. fixed off time of the current regulator (t fo ) : for each of the three highside channels (ch1 - ch3) indi- vidually the fixed off time for all modes with current regulation can be programmed from 100s to 400s. hold current (i hd ) : for each of the three highside channels(ch1 - ch3) individually the hold current value for p&h and hold only current regulation can be programmed. the current range is 0.7a to 2.0a peak time (t p ) : for each of the three highside channels(ch1 - ch3) individually the peak time value for p&h current regulation can be programmed. the time range is 0.8ms to 3.6ms. highside / lowside configuration ( h/l ) : each of the three configurable channels (ch4 ? ch6) can be programmed for use as highside switch or lowside switch. open load and switch bypassed detection activated or deactivated (ol+sb) : for each of the three configurable channels(ch4 ? ch6) the open load and switch bypassed diagnosis can be deacti- vated. in lowside configuration the open load and the short to gnd detection can be deactivated, in highside configuration the open load and short to battery detection. boolean operation (or / and) : for all channels generally the boolean operation of the parallel input signal and the spi bit of the corresponding channel can be defined. overtemperature behavior ( r/l ) : the overtemperature behavior of the channels can be pro- grammed by spi. autorestart or latching overtem perature shutdown can be selected (for all channels the same behavior). diag6 or overtemperature flag (d/f) : with this spi bit the function of the diag6/overtemp pin is defined. this output can work as diagnosis output of channel 6 or as overtemperature flag.
preliminary datasheet TLE6288 r vp2 page 17 13.01.2003 8.4 spi commands command table no command msb 14 13 12 11 10 9 8 7 6 5 4 3 2 1 lsb 1 config. regulator 1 1 0 0 1 mode i pk t fo i hd t p x 2 config. regulator 2 1 0 1 0 mode i pk t fo i hd t p x 3 config. regulator 3 1 0 1 1 mode i pk t fo i hd t p x ch. 6 ch. 5 ch 4 all all diag 6 4 config. ch1 - ch6 1 1 0 0 h/l ol+ sb h/l ol+ sb h/l ol+ sb or/ and r/l d/f x x x 5 set all to default 1 0 0 0 x x x x x x x x x x x x 6 diagnosis only 1 1 1 1 x x x x x x x x x x x x 7 channels on / off 1 1 0 1 ch6 ch5 ch4 ch3 ch2 ch1 x x x x x x legend of spi command table: mode: operation mode of the current regulator: a) no regulation b) hold only c) peak&hold with minimum peak time d) peak&hold with programmed peak time i pk : peak current values 1.2a - 3.6a i hd : hold current values 0.7a - 2a t p : peak time value 0.8ms ? 3.6ms t fo : fixed off time value 100s ? 400s h/l : channel 1-3 in highside or lowside configuration ol+sb : open load detection and switch bypassed detection activated or deactivated or / and : boolean operation (parallel input and corresponding spi bit) r/l : autorestart or latching overtemperature behaviour d/f : diag6/overtemp pin set as diagnosis output of channel 6 or as overtemperature flag ch1-ch6 : on / off information of the output drivers (high active) command description: config. regulator 1-3 : with this command the values for for the current regulation and the functional mode of the channel is written into the internal logic registers. config. ch1- ch6 : this command writes the configuration data of the three configurable channels (4- 6) and sets the boolean operation and overtemperature behavior of all channels. it also and sets the diag6/overtemp. pin to diagnosis of channel 6 or overtemperature flag. set all to default : this command sets all internal logic registers back to default settings. diagnosis only : when this command is sent the 12 data bits are ignored. the internal logic registers are not changed. channels on/off : with this command the spi bits for the on/off information of the 6 channels are set note : specified control words (valid commands) are executed and the diagnosis register is reset after the rising cs edge. not specified control words are not executed (cause no function) and the diagnosis register is not reset after the cs = l ? h signal.
preliminary datasheet TLE6288 r vp2 page 18 13.01.2003 8.5 default settings for the internal logic registers: mode :no regulation peak current (ipeak) :2.4a hold current (ihold) :1a fixed off time (toff) :200s peak time (tpeak) :2.8ms and / or :or autorestart / latch :restart diag6 / temp. fault :diagnosis channel 6 highside / lowside (4-6) :highside open load & sb yes/no (4-6) :yes (diagnosis active) channels 1-6 (on / off) :off spi :all 0 8.6 bit assignment: mode 00 no current regulation 01 hold only 10 p&h minimum peak time 11 p&h with programmed times peak current (i pk ):: : 1.2a 1.8a 2.4a 3.6a 2 bits : 0 0 0 1 1 0 1 1 hold current (i hd ) : 0.7a 1a 1.4a 2a 2 bits : 0 0 0 1 1 0 1 1 fixed off time (t fo ) : 100s 200s 300s 400s 2 bits : 0 0 0 1 1 0 1 1 peak time (t p ) : 0.8 1.2 1.6 2 2.4 2.8 3.2 3.6 [ms] 3 bits : 000 001 010 011 100 101 110 111 boolean operation : or and 1 bit : 0 1 overtemp. behavior : restart latch 1 bit : 0 1 diag6 / overtemp : diag6 overtemp. flag 1 bit : 0 1 highside/lowside : highside lowside 1 bit : 0 1 open load & sb (4-6) : yes no 1 bit : 0 1 default settings are pin bold print.
preliminary datasheet TLE6288 r vp2 page 19 13.01.2003 8.7 spi timing diagrams : input timing diagram (clkprog = l) so valid time waveforms enable and disable time waveforms (clkprog = l) 4 control bit 12 data bit c o n t r o l word 11 10 9 8 7 6 5 4 3 2 1 0 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 cs sclk si so msb lsb t leadl t sckh 0.2v cc t la gl t hl t sckl 0.2 v cc t sul 0.7v cc 0.2v cc cs sclk si 0.7v cc t dt 0.7v cc t vali d sclk cs so t dis 0.2 v cc so 0.2 v cc 0.7 v cc 0.2 v cc so 0.7 v cc 0.2 v cc
preliminary datasheet TLE6288 r vp2 page 20 13.01.2003 input timing diagram (clkprog = h) so valid time waveforms enable and disable time waveforms (clkprog = h) 4 control bit 12 data bit c o n t r o l word 11 10 9 8 7 6 5 4 3 2 1 0 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 cs sclk si so msb lsb t leadh t sckh 0.2v cc t la gh t hh t sck l 0.2 v cc t suh 0.7v cc 0.2v cc cs sclk si 0.7v cc t dt 0.7v cc t valid sclk cs so t dis 0.2 v cc so 0.7 v cc 0.7 v cc 0.2 v cc so 0.7 v cc 0.2 v cc
preliminary datasheet TLE6288 r vp2 page 21 13.01.2003 9 typicel characteristics 9.1 zth diagramm conditions: t case = 125c single channel operation parameters: tp ..... pulse width d ..... duty cycle 1 . 10 5 1 . 10 4 1 . 10 3 0.01 0.1 0.01 0.1 1 10 tp [s] zth [k/w] . d = 0.50 0.20 0.10 0.05 sin g le r t h = 3.1 k/w 0.02
preliminary datasheet TLE6288 r vp2 page 22 13.01.2003 10 package (all dimensions in mm) p-dso 36-12
preliminary datasheet TLE6288 r vp2 page 23 13.01.2003 published by infineon technologies ag , bereichs kommunikation st.-martin-strasse 76, d-81541 mnchen ? infineon technologies ag 1999 all rights reserved. attention please! the information herein is given to describe certain components and shall not be considered as war- ranted characteristics. terms of delivery and rights to technical change reserved. we hereby disclaim any and all warranties, including but not limited to warranties of non-infringement, regarding circuits, descriptions and charts stated herein. infineon technologies is an approved cecc manufacturer. information for further information on technology, delivery te rms and conditions and prices please contact your nearest infineon technologies office in germany or our infineon technologies representatives world- wide (see address list). warnings due to technical requirements components may contain dangerous substances. for information on the types in question please contact your nearest infineon technologies office. infineon technologies components may only be used in life-support devices or systems with the ex- press written approval of infineon technologies, if a failure of such components can reasonably be expected to cause the failure of that life-support device or system, or to affect the safety or effective- ness of that device or system. life support devices or systems are intended to be implanted in the hu- man body, or to support and/or maintain and sustain and/or protect human life. if they fail, it is reason- able to assume that the health of the user or other persons may be endangered.

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